![]() Keywordsīhat GM, Mustafa M, Parah SA, Ahmad J (2010) Field programmable gate array (FPGA) implementation of novel complex PN-code-generator- based data scrambler and descrambler. Vedic multiplication gives an effective result when compared to conventional multipliers. The comparative analysis of Vedic multiplier over the conventional multiplier is implemented using Altera FPGA. The PN sequence generator is implemented using Verilog HDL. In a Vedic multiplier, multiplication is done by using Urdhva Tiryagbhyam sutra, and basic multiplication method is used to design conventional multiplier. In this paper, the approach to generate PN sequence using Vedic multiplier has been proposed. When PN sequence is added to a message signal, it resembles like a noise making it hard to decode and increases the signal bandwidth to utilize the whole spectrum. To provide security to message signal, random noise is added through pseudo-noise (PN) sequence generator. Such data transmission needs some secure techniques to transmit data securely, and one such technique is hiding the transmission data or hiding the message signals. Safe data transmission and reception are important and difficult tasks. Such network has its own specified allotted spectrum for secure communication. In wireless systems like satellite network, mobile communication, or any data transmitted network, a specified band is allotted. ![]() Wireless communication system plays an essential role in data transmission system. ![]()
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